A flash memory is one of the widely used non-volatile memories. Generally, a flash memory chip includes plural memory cells.
FIG. 1 is a schematic cross-sectional view illustrating a memory cell of a conventional non-volatile memory. Generally, charges may be stored in the region between a control gate C and a substrate 13. The operations of the flash memory include a write operation, a read operation and an erase operation. While the write operation or the erase operation is performed, the amount of the charges stored in the region between the control gate C and a substrate 13 may be subjected to a change.
Generally, a threshold voltage (Vth) of the transistor is determined according to the amount of the stored charges. During the write operation, the threshold voltage is changed by applying a positive voltage to the control gate, and the magnitude of the threshold voltage is changed according to the written data. Whereas, during the erase operation, the threshold voltage is changed by applying a negative voltage to the cell. During a read operation, a voltage is applied to the region between the drain terminal D and the source terminal S. When another voltage applied to control gate reaches the threshold voltage, the cell is turned on. According to the magnitude of the threshold voltage, the storing state of the cell can be realized.
FIG. 2 schematically illustrates the change of the threshold voltage distribution curve for the flash memory during the erase operation. In the threshold voltage distribution curve, a greater number of the cells have a median threshold voltage. For example, after a data is written into a single-level cell (SLC) flash memory, the median threshold voltage is V0. For reusing the cells, the threshold voltage (Vth) should be erased to the left of an erase verification voltage Verase by applying a negative voltage to the cells.
Generally, the flash memory includes plural blocks. Each block includes plural pages. The erases operation of the flash memory is performed on blocks. On the other hand, the write operation or the read operation of the flash memory is performed on pages. Typically, the erase operation of the flash memory takes a longer time period than that required by read and write operations. Generally, it takes about several microseconds (μs) to perform the read operation and the write operation of the flash memory, and it takes about several milliseconds (ms) to perform the erase operation. The erase operation for erasing the block of the flash memory is lengthy and consumes a great deal of electric power.
When a controlling circuit issues an erase command to a block, a negative voltage is applied to the cells of the block and the controlling circuit further judges whether the threshold voltages of all cells of the block are lower than the erase verification voltage Verase. If the threshold voltages of all cells of the block are lower than the erase verification voltage Verase, the verifying condition is satisfied. If the verifying condition is not satisfied, the controlling circuit control the corresponding voltages to erase a block again until the threshold voltages of all cells of the block are lower than the erase verification voltage Verase. After the erase operation is completed, the median threshold voltage of the threshold voltage distribution curve is referred as a target voltage Vtarget. Moreover, the time interval from the time point of issuing the erase command to the completion of the erase operation is referred as an erase time period Terase.
FIG. 3 schematically illustrates the change of the operating state of a block of the flash memory according to an erase command. Before the erase operation is performed, the block 15a is referred as a used block. After the erase operation is completed, the block 15b is referred as a free block. As mentioned above, all cells of the block need to be erased and verified. Consequently, as the number of pages contained in the block increases or the number of cells contained in each page increases, the number of cells contained in the block increases. Correspondingly, the erase time period Terase corresponding to the erase command is longer.
Since the erase time period Terase is longer, the performance of the flash memory is gradually deteriorated. Moreover, the flash memory may be erroneously judged as a malfunctioned flash memory by a control chip. If the message about the verifying result is not successfully received by the control chip after the erase command has been issued for a predetermined time period, the control chip will consider the erase command as ineffective. As the number of cells contained in the block increases, the erase time period Terase is correspondingly increased. Under this circumstance, the possibility of erroneously judging the flash memory as the malfunctioned flash memory by the control chip will increase. Therefore, there is a need of providing a memory device and an erase method for performing an erase operation so as to quickly generate free blocks.